Introduction

Over the past several years, Intel has followed an odd path of microprocessor design. On the heels of the success of the P6 core, Intel set two teams in motion - one to work on the NetBurst architecture that would be the foundation of the Pentium 4, and one to work on a low-cost, low power highly integrated core that would eventually be redesigned into the Pentium M. The team eventually charged with designing the Pentium M took a more evolutionary approach building off of the strengths of the P6 architecture, while the NetBurst team preferred a radical departure from Intel's previously most successful architecture at the time.

We all know how this story ends; as NetBurst evolved, so did the underlying architecture of the Pentium M. Dothan was the first tweak of the Pentium M and it was mostly a clean up job to fix some performance issues with the original core. Higher clock speeds, more cache, and slight increases in IPC were on Dothan's CV.

Intel's Israel Development Center (IDC) then took Dothan and re-architected it to be a native dual core solution, complete with a shared L2 cache, the first of its type for an Intel processor. The Dothan to Yonah progression was far more significant than the move from Banias to Dothan, not just because Yonah was dual core but also because of the many architectural improvements that went into Yonah.

The next step Intel took is one we're all familiar with, and involves the most radical design change of the Pentium M's short lived history; Intel took Yonah and made it wider, deeper, and far more efficient. Out came the Core 2 line of processors and with it, Intel regained the undisputed performance crown it hadn't seen ever since the debut of AMD's Athlon 64.

While many argued that Banias, the first Pentium M core, was merely a modern take on the P6 architecture it's hard to see much in common between today's Core 2 and the 11 year old Pentium Pro. The P6 core was a starting point for a long line of evolution that brought Intel to where it is today.

AMD took a far more conservative approach over the past several years; it all started with the success of the K7 core, effectively a wider, faster, competitor to later versions of Intel's P6 architecture. While one of Intel's teams was busy making radical departures from anything AMD or Intel had done in the past, AMD didn't have the luxury of running two large scale microprocessor projects in tandem. The solution was to take the K7 core and improve on it, rather than taking a risky step in a different direction.

The K8 core was born as an evolution of the K7; with a slightly deeper pipeline, slight architectural improvements and an integrated Northbridge, the K8 was a pretty major evolutionary step for AMD over the K7. In fact, it took the Core 2 Duo to truly outperform the K8 core across the board, although Dothan and Yonah came quite close in certain applications.

AMD had worked on dramatic successors to the K8, rumored to be K9 and K10, but both appeared to be scrapped or at least focus was shifted away from them in favor of a more evolutionary take on the K8 architecture. The main difference here that allowed Intel to catch up to AMD's performance is that while Intel's Pentium 4 team was operating on the usual schedule of a 5-year micro-architecture cycle, the Pentium M team at IDC was updating its architecture every year. Banias, Dothan, Yonah and Merom/Conroe all happened in a period of four years, and during that same time AMD's K8 remained unchanged.

If Intel had continued down the Pentium 4/NetBurst route, sticking to the usual 5-year design cycle would have probably worked just fine for AMD but Intel had the luxury of having two major micro-processor teams working in parallel, one of which had a much better idea. Luckily it would seem that AMD realized it needed to compete with Intel using smaller evolutionary steps every couple of years rather than leaving an architecture relatively untouched for 4 - 5 years and thus the Barcelona project was created. Although it's set to debut around a year after Intel's Core 2 Duo that swiped the performance crown, Barcelona is AMD's best chance at remaining competitive.

Barcelona's window of opportunity is slim, depending mostly on how Intel's transition to 45nm goes. Publicly Intel has stated that its architectural update to Core 2, codenamed Penryn, will begin shipping by the end of 2007. However, current roadmaps show availability at sometime in 2008 with no word on when significant quantities will be available. Should Intel take longer than expected with the move to its 45nm Penryn core, Barcelona's mid-2007 launch on servers and Q3 '07 launch for desktops may come at a relatively quiet time for Intel.

The Chip
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  • chucky2 - Friday, March 02, 2007 - link

    Can you post the link that originates at AMD's own website then that says specifically that AM2+ CPU's are guaranteed to work - understandably maybe not supporting every new feature - in current AM2 boards?

    Not a news post from DailyTech, The Inquirer, Toms, whatever...one that's on AMD's site itself.

    And No, AMD could make AM2+ completely incompatible with current AM2 boards and they probably wouldn't see much drop if at all from the large OEM's. The large OEM's would just ensure that when the AM2+ CPU's came in, AM2+ motherboards would likewise come in.

    Believe me, I want to see the link...because I'm desperately awaiting 690G or MCP68, whichever comes first (which is probably MCP68 at the pace AMD is moving on 690G).

    Chuck
    Reply
  • yacoub - Thursday, March 01, 2007 - link

    quote:

    In order to keep die sizes manageable, AMD constructed its quad-core Barcelona out of four cores each with a 128KB L1 and 512KB L2,


    You say 128kb L1 per core but the diagram image just beneath that text shows a 64bit L1 cache. Please confirm which it is.

    Thanks.

    Awesome article, btw. Seems like quite a significant group of changes to the CPU. Looking forward to seeing how it stacks up against the best Quad Core2 Intel can offer. =)
    Reply
  • yacoub - Thursday, March 01, 2007 - link

    also, please forgive my hasty typing - I wrote "128kb" and "64bit" - I meant "128KB" and "64KB" Reply
  • JarredWalton - Thursday, March 01, 2007 - link

    L1 is 128K total - 64K data and 64K instruction. Reply
  • Beenthere - Thursday, March 01, 2007 - link

    AMD doesn't do knee-jerk reactions like Intel because AMD has superior products. AMD continues to take market share from Intel in every segment and Barcelona will continue that trend. Barcelona looks to be every bit as superior to Intel's hacked/patched/glued together chips as Opteron was when introduced. Intel's chips depend on huge cache size for their performance and that crutch won't work after the intro of Barcelona.

    For those without a clue, AMD didn't start design of Barcelona last week or last year. It's been in the development pipeline for many years and thr performance will demonstrate exactly why AMD's long term platform stability is the right choice for most enterprise buyers. Intel is gonna feel the pain again.
    Reply
  • Roy2001 - Thursday, March 01, 2007 - link

    Facts please, no BS. Reply
  • zsdersw - Thursday, March 01, 2007 - link

    Idiocy incarnate. Reply
  • Regs - Thursday, March 01, 2007 - link

    AMD, like Intel, start numerious projects. Just not all of them get to this finish line. Actually a lot of them don't even reach the end of the planning phase before being scratched.

    As for Intel and their large caches...well I'd say it's amazing how half their die (if not more) is used for cache and still had enough space for all the core logic that's kicking the crap out of the K8 now.

    Common sense!
    Reply
  • erwos - Thursday, March 01, 2007 - link

    Looks like some good improvements coming down the pipe. The cache size issue makes me nervous, though - 512kb per core is starting to look a little antiquated, and there's no information about the bandwidth to the L3 cache (which, presumably, is slower than L2). Reply
  • SmokeRngs - Thursday, March 01, 2007 - link

    In the past, AMD did not need the large cache sizes that Intel did for their processors. This was very obvious in regards to the Netburst architecture. However, while Core2 is much better than Netburst there are still disadvantages for Intel.

    I'll explain a little background as far as I understand it. In the K7 and Netburst days, Intel had to have the cache to make up for their long pipeline. Branch mispredictions are going to happen and the penalty on the long pipeline of the Netburst processors hurt their IPC badly. The shorter pipeline on the K7 did not have the same performance penalty due to the shorter pipeline. With K8, the on die memory controller also negated the need for large L2 caches due to the reduced latency when accessing main memory. This has been one of the major performance aspects for the K8 architecture.

    The Core2 architecture obviously does not have the on die memory controller so the need for larger caches is still present and Intel sees improvement due to the larger caches. Barcelona still has the on die memory controller and the previous efficiency is still there and still negates the need for large caches. This is just the difference between architectures. While having a larger cache on the K8 did improve performance some in some usage scenarios, it wasn't on the same scale as the improvements Intel received with a larger cache.

    AMD can't compete with Intel in regards to cache size. However, other architecture differences make up for the lack of large amounts of cache. Barcelona having a smaller cache does not seem to be a big problem. If it was a big problem, AMD probably would have gone with a larger cache to get the extra performance. Bigger does not always mean better or at least enough better to warrant the extra.

    Smaller cache will mean fewer transistors which should mean better yields, lower power consumption and cheaper to produce.
    Reply

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