It's taken AMD almost the entire life-span of the Athlon 64, but Intel is finally on the run. Pick whatever measure of success you'd like, whether it is performance benchmarks, the Dell announcement, or being publicly accepted as a threat - AMD has done it. It's because of AMD's extremely successful uphill battle against Intel these past few years that we've had such high expectations from the company. So when Intel first started talking about its new Core architecture, we turned to AMD for a response that it surely must have had in the works for years, but as you all know we came up empty handed.

Only recently has AMD begun talking about what's coming next, and it will divulge even more information in the following weeks. The problem is that the architectural revisions to K8 that AMD is finally talking about now are still things we will see in the 2007 - 2008 time frame, while Intel's Core architecture is still on schedule to be a reality for 2006. What AMD does have planned to keep itself afloat during 2006 and until the new K8L core debuts is a brand new platform: Socket-AM2.

The long awaited Socket-AM2 platform marks the beginning of AMD's transition to DDR2 memory. If you'll remember, Intel made this transition about two years ago with the introduction of its 925X and 915 series of chipsets. The move to DDR2 proved to yield very little in the way of performance, but it was necessary as Intel was able to drive enough quantity of DDR2 in order to make the cost reasonable today. With DDR2 prices low enough, and availability high enough, AMD was poised to take advantage of Intel's work in establishing DDR2 as a desktop memory standard and support it on a new platform.

In AMD's uncharacteristic silence over the past several months, performance expectations for DDR2 on Socket-AM2 remained completely unset. A little over a month ago we previewed the Socket-AM2 platform and concluded that even when paired with DDR2-800, you shouldn't expect a performance increase from AM2. While AMD didn't publicly confirm or refute our benchmarks, all of its partners were in agreement with the results we had seen. Today, with final AM2 hardware in our hands, we're able to see exactly how far the platform has come in the month since we last looked at it.

AM2 in Detail
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  • soydios - Tuesday, May 23, 2006 - link

    AMD motherboards are less expensive because they don't have to put in a memory controller.

    AMD processors are more expensive for 2 reasons:
    - integrated memory controller takes up more die space (offset by cheaper motherboard)
    - AMD is still using 90nm on 200mm wafers, while Intel is using 65nm on 300mm wafers (Intel gets more CPUs per wafer bigtime)
    Reply
  • peternelson - Tuesday, May 23, 2006 - link


    Sempron AM2 can do memory up to DDR2-667

    Dualcore AM2 can do memory up to DDR2-800

    However, PLEASE CHECK SINGLE CORE MEMORY SPEED (multiplier issues aside) which you say limited to 667 whereas I got the impression they can also do 800 like dualcores. Correct as necessary.
    Reply
  • smitty3268 - Tuesday, May 23, 2006 - link

    I accidentally hit the "not worth reading" button, so I'm writing this comment to undo it :) Reply
  • fikimiki - Tuesday, May 23, 2006 - link

    There are a couple of reasons for that:
    - K8L photo had a Z-RAM implemented, so they are using this kind of cache for a quite long time.
    - Shared L3 should help Athlon64 in matching Super-Pi and overall performance.
    - Usage of Z-RAM will reduce cache die size by 75% with no architectural changes.

    So FX-64 to beat fastest Core 2 just needs 4MB of cache...
    Easy trick but can be useful to survive till 65nm production...
    Reply
  • Questar - Tuesday, May 23, 2006 - link

    quote:

    K8L photo had a Z-RAM implemented, so they are using this kind of cache for a quite long time.


    It's not going to be Z-RAM. Z-RAM won't even be in K8L.

    “We’ve looked at data from Innovative Silicon and it looks very promising. We still need to assure ourselves that this will work in our own application. We need to see how it scales and we need to make our own test vehicles,”

    Jones, an executive experienced in intellectual property licensing, also declined to comment on AMD’s timetable for introduction of Z-RAM but offered a more general perspective. “In the past it has been two years from when you sign a deal to when it is in production.”


    http://www.eetimes.com/news/latest/showArticle.jht...">http://www.eetimes.com/news/latest/showArticle.jht...
    Reply
  • munky - Tuesday, May 23, 2006 - link

    I think the June trick AMD will pull out is the Clearspeed coprocessor. It definitely won't affect many users, but for those who do invest in the technology, it could provide a decent boost in number crunching power. Reply
  • peternelson - Tuesday, May 23, 2006 - link


    Clearspeed are working on being one acceleration solution, yes, but the already launched acceleration on socket 940 is companies offering plug in Xilinx4 FPGA on hypertransport.

    I hope that gets re-engineered onto socket F pretty quickly. We may see announcements once socket F is actually launched in July.
    Reply
  • darkdemyze - Tuesday, May 23, 2006 - link

    z-ram isn't due for AMD procs for quite some time, I doubt this is their plan for June.. Reply
  • mlittl3 - Tuesday, May 23, 2006 - link

    Basically this is what I said above for my guess of the "trick" AMD will use. Anand said it will only affect some high-end users, read FX series so it can't be price cuts as some have suggested (that would effect everyone). Adding L3 cache is the only performance improvement I can think of that doesn't require changing the microarchitecture of the cores (well at least not a big change).

    However, TDP is still an issue here as someone above suggested. I don't know how much more power it takes to run L3 cache. Last time AMD did it was on K6 and power wasn't really measured back then.

    By the way, please ignore Questar's comment below about z-ram being pig slow. I really don't think he knows what he is talking about. /shields eyes from incoming Questar flame
    Reply
  • johnsonx - Wednesday, May 24, 2006 - link

    K6-III did not have L3 cache. It had L2 cache, making the cache that all socket-7 boards had then an L3 cache.

    So, let's stop saying things like 'AMD hasn't done L3 cache since K6-III', etc.
    Reply

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