Introduction

With this week's introduction of the x52 line of Opteron processors, AMD is giving us a little look into the future of their Athlon 64 line. As mentioned in our article on Monday, the new 2.6GHz speed grade is also introducing the new E4 stepping, which adds SSE3 support. The new Opteron also received a face lift in that it is fabbed on a 90nm process, runs coherent HT links at 1GHz, and comes in a shiny new organic package rather than the older ceramic.

The goal of this article is to bring out a quick look at what SSE3 brings to the table for Opteron and the future revision E Athlon 64 cores. As desktop parts do not enable coherent HT links at all, the 1GHz support won't matter. Also, the newer A64 parts are already 90nm on organic packages. Other than the usual small tweaks we see between steppings, the only thing that will be new across the board for K8 processors is SSE3.

What exactly is SSE3? Intel introduced SSE3 as Prescott New Instructions last year. These instructions are generally additions to the SIMD (single instruction multiple data) capabilities of the processor. SIMD processing is based on the idea that sometimes processors must take large amounts of data and perform similar operations across the entire set. This lends itself well to things like audio and video processing. In these areas of computing, large amounts of data flow through the processor, undergoing roughly the same operations, in preparation for display. The philosophy behind SIMD lends itself well to graphics as well. Modern graphics cores incorporate many SIMD processing units in order to churn through vector and pixel data as fast as possible. SIMD processing has also largely overshadowed the use of the x87 floating point unit on x86 processors. Because of this, it is advantageous for AMD to support the extensions to SIMD Intel makes as quickly as possible.

With SSE3, Intel added 10 new instructions targeted at SIMD as well as 3 other instructions that don't touch the SSE registers (fisttp, monitor, mwait). Here's a brief list of SSE3 instructions and what they are for:
x87 floating point to integer conversion (fisttp)
Complex arithmetic (addsubps, addsubpd, movsldup, movshdup, movddup)
Video encoding (lddqu)
Graphics (haddps, hsubps, haddpd, hsubpd)
Thread synchronization (monitor, mwait)
The float to integer conversion is rather obvious in function, but some of the other instructions are a little mysterious. The complex math instructions extend functionality for imaginary numbers. The hadd and hsub instructions are horizontal additions and horizontal subtractions. These allow faster processing of data stored "horizontally" in (for example) vertex arrays. Here is a 4-element array of vertex structures.
x1 y1 z1 w1 | x2 y2 z2 w2 | x3 y3 z3 w3 | x4 y4 z4 w4
SSE and SSE2 are organized such that performance is better when processing vertical data, or structures that contain arrays; for example, a vertex structure with 4-element arrays for each component:
x1 x2 x3 x4
y1 y2 y3 y4
z1 z2 z3 z4
w1 w2 w3 w4
Generally, the preferred organizational method for vertecies is the former. Under SSE2, the compiler (or very unfortunate programmer) would have to reorganize the data during processing.

The lddqu instruction is designed to reduce the impact of 128bit unaligned memory accesses. As unaligned loads happen quite often in video processing, the lddqu instruction is designed to load 256bits of data aligned on a 16byte boundary. The instruction also takes care of extracting the correct 16bytes (as requested) from the 32byte block. Under SSE2, 64bit loads are executed and then the data is recombined.

In order to test these features as implemented by AMD, we tested an Opteron 250 against an Opteron 252. We were able to use crystalcpuid to set the multiplier of the Opteron 252 (though powernow!) to 12 in order to match the 2.4GHz of the Opteron 250. This way, we'll have a direct comparison of the two architectures.

We ran both processors in HP's wx9300 workstation. We used a single CPU configuration and 4x 512MB of RAM at 3:3:3:8. Windows XP SP2 was used in our tests. In an MP environment (with more memory bandwidth), the Opteron has a greater potential for improvement with SSE3. Unfortunately, we were unable to perform a direct comparison of the older and newer cores under a DP configuration. Attempting to use powernow! to adjust the multiplier with more than 1 processor installed resulted in a BSOD (machine check exception).

SSE3 Performance Analysis
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  • Beenthere - Thursday, February 17, 2005 - link

    The only reason Intel created SSE3 was to have bogus benchmarks to fool naive consumers. There is no significant performance advanatage in any application. When you're Intel and you can provide incentives for benchmarks to be written to your liking to show a fantasy performance advantage, and your product line is obsolete and your market share is dropping, you do whatever you can to deceive consumers and hacks. AMD included SSE3 so Intel couldn't use the bogus benchmarks for misleading marketing purposes.

    This is no different than when MICROSUCKS paid to have benchmarks run that showed Win2000 to be faster than NT4 when in fact it is NOT in actual practice.

    SOD, DD

    Time for PC users to become a little more knowledgeable on the scams being used by dishonest companies to hawk inferior products.
    Reply
  • Carfax - Thursday, February 17, 2005 - link

    Hey Derek. Could you test SSE2 performance aswell?

    As it has been mentioned, the E stepping was rumored to possess a better SSE2 implementation.
    Reply
  • iwodo - Thursday, February 17, 2005 - link

    I always thought E core stepping is going to bring many things new on the table.

    Improved memory contoller, that is suppose to be faster and have better compbality.

    Improved SSE2 core - More performance.

    Better Cache Latency

    SIO - Lower TDP...........

    Where is all these in the review? Or are they just total rumors or They are not avalible on Opertron?
    Reply
  • DerekWilson - Thursday, February 17, 2005 - link

    Oh, but back on topic... I've had a lot of emails about AMD simply mapping SSE3 functionality to SSE2 (or even x87) hardware. This would be a very bad idea for AMD and doesn't look like what they are doing.

    If we had seen AMD impliment the entire SSE3 instruction set as essentially macros for SSE2 we would likely have seen a performance drop. There's not an easy way to just map some of the instructions, as optimal performance would require a recompile. We actually saw a performance gain in our synthetic benchmark that used some of the floating point instructions.

    It is possible some instructions could be treated this way. For example, there's no reason the code that uses a standard method to load 16 bytes (that may or may not be unaligned) and lddqu should look different.
    Reply
  • DerekWilson - Thursday, February 17, 2005 - link

    No one uese Opteron?

    http://www.anandtech.com/IT/showdoc.aspx?i=2173

    Also, if you need 4P or more, there's no reason to limit yourself by going with Intel's FSB implimentation -- It really hurts the performance of the system:

    http://www.anandtech.com/IT/showdoc.aspx?i=1982
    Reply
  • xsilver - Thursday, February 17, 2005 - link

    old habit ?
    Its called perception lag -- when perception (of intel being good) needs to catch up to reality .... oh and also blame it on companies like dell etc.
    Reply
  • Brunnis - Thursday, February 17, 2005 - link

    bigpow: But then again, I wouldn't go with Opteron too.

    Why not? Opteron is better than Xeon in many areas.

    A large reason why many companies don't use much else than Intel products are probably because of old habit. That's just stupid, in my opinion, but everyone's different...
    Reply
  • sandorski - Thursday, February 17, 2005 - link

    Bigpow: Opteron has gone from 0-10% marketshare in he server space. So it's not surprising that you nor anyone you know has them, but they are being used and last I heard they were still gaining Marketshare. Reply
  • Samadhi - Thursday, February 17, 2005 - link

    It has been written in a number of places that as well as adding SSE3 units the SSE2 units were to be improved in the latest chip revision.

    Any chance we could get some SSE2 vs SSE2 results for the two processors tested in this article?
    Reply
  • SkAiN - Thursday, February 17, 2005 - link

    Sorry for the blank post.

    When I first began reading this article, I became excited, looking forward to seeing the benchmarks this "upgrade" was supposed to bring, especially in the area of encoding.

    Then I saw the benchmarks.

    Seriously, it looks as if AMD is getting the short end of the stick when it comes to the cross-licensing deal with Intel. Intel gets awesome new architechture, A64's get Intel's bogus hype...
    Reply

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