Rambus in Cell

Rambus just proudly announced that their XDR memory interface would be used in the elusive Cell processor, being announced today at the International Solid State Circuits Society conference (ISSCC) in San Francisco. 

There's not much surprise that Rambus was selected to be involved with the Cell project, given their previous history with Sony and the Playstation 2, as well as their ability to deliver extremely high bandwidth memory devices on very low pincounts.  Sony and Toshiba also signed a licensing agreement back at the start of 2003 to work on the Cell project. 

For years Rambus has been telling us that they've been working with GPU manufacturers on getting their high-bandwidth designs into future GPU architectures, and their design win with Sony may just be the key to getting XDR on PC graphics cards as well - especially since NVIDIA handled GPU design for the Playstation 3.

The other interesting part of Rambus' announcement is that they are also responsible for the Cell processor interfaces - it's connection to the outside world (or to other Cell processors).  Rambus has had a serial processor bus interface in their IP repertoire for quite some time now, called FlexIO.  FlexIO is being used as the processor interface standard for Cell.

FlexIO implements two very important features - what Rambus is calling FlexPhase, and DRSL (Differential Rambus Signaling Level).  Normally when traces (wires on a PCB) are laid out, they have to be arranged in such a way that all of the traces going to the same chip have equivalent lengths.  As buses get wider and board designs become more complex, trace routing becomes a very serious engineering problem.  Because of the need to match trace lengths, you'll often see traces wrapped around themselves or laid out in artificially long paths to make sure that the signals they carry don't arrive sooner than they should.  FlexPhase is a technology that allows for on-chip data and clock alignment for signals that don't all arrive at the same time, allowing for traces that aren't matched in length on the PCB.  There is an added element of latency introduced by FlexPhase as the chip must handle all clock and data adjustments that are out of phase, but the idea is that what you lose in latency do to FlexPhase, you make up for it in design simplicity, potentially allowing for higher data rates. 

The next technology that FlexIO enables is DRSL with LVDS (Low Voltage Differential Signaling), which is a technology similar to what Intel uses in the Pentium 4 to reduce power consumption of their high-speed ALUs.  We will actually explain the technology in greater detail later on this week in unrelated coverage, but the basic idea is as follows: normally the lower the voltage you run your interfaces at, the more difficult it becomes to detect an electrical "high" from an electrical "low."  The reason being that it is quite easy to tell a 5V signal from a 0V signal, but telling a 0.9V signal from a 0V signal becomes much more difficult.  DRSL instead takes the difference between two voltage lines with a very low voltage difference and uses that difference for signaling.  By using low signal voltages, you can ensure that even though you may have a high speed bus, power consumption is kept to a minimum.  The technology isn't  quite sophisticated enough to make the transition to the mobile world, but with some additional circuitry to dynamically enable/disable interface pins it would be quite easy to apply FlexIO to mobile applications of the Cell architecture.

The culmination of these two features is that FlexIO offers up to 8.0GHz data rates based off of a 400 - 800MHz interface clock.  It is worth noting that such a high input clock frequency would inherently require some pretty sophisticated technologies to implement.

Because Rambus is providing both the memory and processor I/O interfaces for Cell, it's not too surprising that 90% of the Cell's signaling pins are using Rambus interfaces.  Looking at any modern day microprocessor, the biggest use of signaling pins goes to things like enabling multiprocessor support, a chipset interface and a memory interface (obviously varying based on the type of processor we're talking about) - so Rambus' statistics aren't too surprising. 

There are still some unanswered questions - mainly whether or not FlexIO will be used to interface with NVIDIA's graphics core (which we're guessing it will) and whether or not XDR will be used for the GPU's local memory (which we're also guessing it will).  Given the negative impression of Rambus amongst PC enthusiasts, a successful implementation in PS3 and with NVIDIA's GPU could mean a virtual second chance for Rambus in the PC market.

Intel’s Happy about Dual Core
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  • IntelUser2000 - Tuesday, February 08, 2005 - link

    #7

    Actually it seems Prescott doesn't want more memory bandwidth AT ALL, so XDR would do nothing. It seems Prescott is designed for nothing but clock speed scaling, it cares nothing about cache, nothing about bandwidth, perfect for scaling clock speeds since increase in clock speed=more bandwidth requirement but since Prescott doesn't care, its all good. Its all moot now though.

    If you want to see that go to www.x86-secret.com for reviews. The 2MB cache Prescotts do absolutely nothing for performance while costing 20% more. So does the 3.73GHz Prescott 2M EE, even with 1066MHz bus its slower than 3.46GHz Northwood 2MB L3 1066MHz bus EE.
    Reply
  • stevty2889 - Monday, February 07, 2005 - link

    I was worried for a second there when the mentioned rambus and Intel dual core in the heading together..although it would be interesting to see how much the Prescott would like all the bandwidth XDR ram could provide.. Reply
  • JarredWalton - Monday, February 07, 2005 - link

    Don't get so down on Rambus, guys. Did they cause some trouble initially? Yes. But then, AMD, Intel, ATI, NVIDIA, VIA.... Just about any major technology company has made a product that people didn't like, or one that was timed poorly, offered less than acceptable performance, etc. Rambus is actually some pretty interesting stuff at the low level. The basic point of any memory technology was covered in the memory article we published a while ago:

    "Any design can be modified to work with higher or lower latencies; it is but one facet of the overall goal which needs to be addressed."

    That is the heart of the whole Rambus problem. The Pentium 3 was not designed AT ALL to make use of Rambus. It couldn't really use DDR well either, although Intel never pursued that. The Pentium 4 actually made very good use of Rambus, and up until the 865/875 were released, the Rambus chipsets (850/850E) were the fastest performing P4 chipsets. Graphics chips in particular are usually quite happy with higher latencies as long as they also get higher bandwidth. XDR certainly offers that!

    XDR at 400 MHz octal-pumped gives 3.2 GHz per pin, so a 64-bit interface can provide a whopping 25.6 GB/s of bandwidth. Yeah, the 256-bit interface on an X850XT or 6800U provides more total bandwidth, but only by using four times as many pins. Considering most graphics chips with 64-bit DDR solutions are only providing 3.2 GB/s of bandwidth, XDR is very interesting.

    We'll see how the actual implementation turns out. Personally, I would not be at all surprised to see NVIDIA try XDR with an upcoming GPU. The "royalty problem" of Rambus really isn't that big of a deal in the larger scheme of things. Remember that Pentium, Athlon, Opteron, etc. are all proprietary technologies that have a built-in "royalty" to their designers.
    Reply
  • knitecrow - Monday, February 07, 2005 - link

    The flexIO sounds interesting, does any one acutally know what the bandwidth is like for such an IO and how does it compare to hypertransport?

    Reply
  • Brian23 - Monday, February 07, 2005 - link

    #2, Who says that I'm going to connect my PS3 to the internet? If I just use it as a game machine, sony can't do anything with my hardware. Even if I did connect it to the internet, I HIGHLY doubt that there is a backdoor for sony to do stuff to it. It would just be a hole for someone to exploit. Reply
  • xsilver - Monday, February 07, 2005 - link

    is there any word / ideas on the possbility of overclocking in the dual core p4's ? running 800mhz fsb may not make that easy but........

    and also with rambus I think a lot of people will take the stance of "I'll believe it when I see it" since so many people still have a bad taste in their mouths :)
    Reply
  • DestruyaUR - Monday, February 07, 2005 - link

    Anyone else think it's kind of odd that Cells are using Rambus, a technology we were ALSO told was going to revolutionize computing as we then knew it?

    Also, I'd like to know - since Cell's power depends on interconnectivity, is there a central compromisable link to control the network it'll create.

    A conspiracy theorist could almost make the case that Sony would have access to one of, if not THE, most powerful supercomputer in the world...and if not them, whoever could compromise the net.
    Reply
  • MarchTheMonth - Monday, February 07, 2005 - link

    I really think amd will release a press info tomorrow that they will have dual core opterons and athlon64's ready 2 days before intel will have their dualies out. Reply

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