Introduction

We have been patiently waiting this Fall's Intel Developer Forum for quite some time. Rumors that Intel would host a live dual core demonstration have kept our interest piqued. It's tough to deal with that guilty kind of excitement, the kind where you hope for something you couldn't expect and the very hope itself seems to crush the chances of its fulfillment. After all the waiting, we can say that the rumors were true: Intel just finished demonstrating a running dual core Montecito Itanium processor. This is a good thing and a bad thing, but we'll talk more about that in a minute.



Amidst a few new things, we did hear plenty of the same old thing from Intel about technologies that are either here now, or years off into the future (with no new insight). For instance, much of the keynote covered Hyperthreading, EM64T, and Wifi, or focused on previously demonstrated technologies like Vanderpool. While all of these things are fun and interesting, we've already heard about them time and time again. Granted, the Vanderpool demo was from a business perspective rather than a home user perspective. It's cool to see 4 different hardware virtualized systems running on one computer, but the concept's potential and its uses have been explored previously via software such as VMWare. But buried in the presentation were a few tidbits we did find useful, and that's what where here to bring you today.

The following pages will cover the the new things mentioned at the opening keynote, as well as the growing importance Intel places on parallelism.
What's New From the Keynote
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  • Lonyo - Wednesday, September 08, 2004 - link

    We knew that they woul dhave 24MB of cache a while ago.
    There was a post on the Anandtech forums asking why you would need such a large amount of cache.
    Reply
  • kherman - Wednesday, September 08, 2004 - link

    So, am I the only one that noticed that EACH PROCESOR HAS 24 MEG OF CACHE ON IT!

    First image on page 3:
    http://www.anandtech.com/tradeshows/showdoc.aspx?i...
    Reply
  • ysrgrathe - Wednesday, September 08, 2004 - link

    iCube is supposed to be presenting their NMP-5000A network media player at the IDF. They won an award last year for their NMP-4000 model, which has also received a lot of positive reviews. I'm interested to know more; iCube has nothing on their site other than a press release about the IDF presentation an a picture showing dual antennas.

    From last year's timeline I would expect the product to launch around Christmas; would be nice to have some info before then. Anyone at the convention hear anything?
    Reply
  • JarredWalton - Wednesday, September 08, 2004 - link

    ^^^ This is why you shouldn't do drugs, kids. Reply
  • AMDjihad - Wednesday, September 08, 2004 - link

    AHAHAH> INtel loses like a faceusut. AHAHA. Whorlovas. Intel loses. I agrre witgb alkb of you. Intel sucks. HAHAHA> OPertin ins bwext at everythoing. Hah wether simulation.s I can do that. HAhahha. Reply
  • TrogdorJW - Wednesday, September 08, 2004 - link

    #12 - Itanium 2 can issue up to 8 instructions per clock, but stalls on one set of instructions can still occur. If you have hyper-threading, you have more potential to fill all of the available issue slots. That's why the POWER5 chip from IBM also has a version of hyperthreading, although I believe IBM calls it "symmetric multi-threading" (SMT). Oh, and Itanium also has more FP/SSE execution units than the P4/Xeon, which is why it has such "kick booty FP".

    #8 - That really didn't make much sense, partly due to the incorrect use of the Enter key. But let's address this: "Intel has not had a demonstrable lead in design or manufacturing in several years. They have only been maintaining parity with the competition. They intially argued against the need for .13 micron and smaller die shrink, they followed the lead of IBM and AMD. And followed again when copper replaced aluminum in the CPU." Ugh, where to begin...

    Okay, let's make this clear. Intel has never argued against .13 micron or any other process shrinks. They have said at times that it was not necessary *YET*, and that they would pursue it in the future. This happened with copper interconnects (AMD used them in .18 micron while Intel waited until late in their .13 micron use), and it happened with x86-64. Don't confuse "we aren't doing that yet" with "we aren't pursuing that *ever*".

    You can make a case for some issues with their designs of late, but as far as technology? We've seen 90 nm parts from Intel for almost a year now (more if you count early samples), while AMD is only just starting to ship them. IBM went with SOI first and Intel went with strained silicon. They're both pushing the process technology in different ways. To say Intel hasn't been perfect is absolutely valid, but to say they're failing completely (which seems to be the gist of your post) is taking it way too far.

    Just my opinion here, of course.
    Reply
  • mkruer - Tuesday, September 07, 2004 - link

    The only advantade that the Itanic has in computer operations is that is has a kick booty FP operation. problem is that most progrmas use limited floating point. on top of that I would not be to supprised to see the FP core migrating into the Xeon, or what ever intel is going to call their next gen chip Reply
  • sprockkets - Tuesday, September 07, 2004 - link

    Big deal, 1.7 billion transistors, probably 95% of that is just cache memory.

    Again, why would Itaniums need Hyperthreading? If your EPIC code alreay is made to process so many instructions at once in parallel, then how is hypthreading going to make any difference?
    Reply
  • ksherman - Tuesday, September 07, 2004 - link

    sorry, my post was intended for #8 not #9 Reply
  • ksherman - Tuesday, September 07, 2004 - link

    ^ half that didnt make sense...
    and I am sure that 4 dual core opterons could probably do real time weather simulations too, its not an Intel exclusive capability...
    Reply

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