AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis
by Ian Cutress on June 20, 2017 4:00 PM EST- Posted in
- CPUs
- AMD
- Enterprise CPUs
- EPYC
- Whitehaven
- 1P
- 2P
With recent fears about security, and given that these processors are aiming to go to the Enterprise space, AMD had to dedicate some time to explaining how secure the new platform is. AMD has had its Secure Processor in several CPUs at this point: a 32-bit ARM Cortex-A5 acting as a microcontroller that runs a secure OS/kernel with secure off-chip storage for firmware and data – this helps provide cryptographic functionality for secure key generation and key management. This starts with hardware validated boot (TPM), but includes Secure Memory Encryption and Secure Encrypted Virtualization.
Encryption starts at the DRAM level, with an AES-128 engine directly attached to the MMU. This is designed to protect against physical memory attacks, with each VM and Hypervisor able to generate a separate key for their environment. The OS or Hypervisor can choose which pages to encrypt via page tables, and the DMA engines can provide support for external devices such as network storage and graphics cards to access encrypted pages.
Because each VM or container can obtain its own encryption key, this isolates them from each other, protecting against cross-contamination. It also allows unencrypted VMs to run alongside encrypted ones, removing the all-or-nothing scenario. The keys are transparent to the VMs themselves, managed by the protected hypervisor. It all integrates with existing AMD-V technology.
Alongside this are direct RAS features in the core, with the L1 data cache using SEC-DED ECC and L2/L3 caches using DEC-TED ECC. The DRAM support involves x4 DRAM device failure correction with addr/cmd parity and write CRC with replay. Data poisoning is handled with reporting and a machine check recovery mode. The Infinity Fabric between dies and between sockets is also link-packet CRC backed with retry.
One element that was not discussed is live VM migration across encrypted environments. We fully suspect that an AMD-to-AMD live migration be feasible, although an AMD-to-Intel or Intel-to-AMD will have issues, given that each microarchitecture has unique implementations of certain commands.
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vladx - Tuesday, June 20, 2017 - link
Lol what a shady move from AMD to reduce Intel CPUs' benchmark numbers in order to make Epyc appear better than it actually is, never change AMD never change.tamalero - Tuesday, June 20, 2017 - link
COUGH COUGH COUGH Yeah, because Intel never has done the same.. COUGH COUGH COUGH..https://www.extremetech.com/computing/193480-intel...
https://www.theinquirer.net/inquirer/news/1567108/...
vladx - Tuesday, June 20, 2017 - link
First there's a big difference between straight-out misleading customers and making backside deals with OEMs, and second that compiler crippling stuff is still unsubstantiated and Intel has no obligation towards AMD with regards to Intel's own compiler. AMD should make their own compiler that offers better or at least equal to Intel's own optimizations instead of using disgraceful tactics like that.galahad05 - Wednesday, June 21, 2017 - link
How's Intel doing fighting that enormous fine the EU levied against it for their underhanded tactics against AMD years ago?vladx - Wednesday, June 21, 2017 - link
Afaik they paid billions which AMD squandered like it was nothing.galahad05 - Wednesday, June 21, 2017 - link
Um.... Where to begin?The fine doesn't go to AMD. It goes to the European Commission....
So far Intel's lawyers have held the EC at bay all these years. Which technically means Intel got away with it....
Such is life.
Mugur - Wednesday, June 21, 2017 - link
What I don't understand from the slide with the prices: it looks like the 1P cpu is priced higher ($750 versus $650) than the 2P counterpart? I assume that any 2P cpu could be used in a 1P motherboard, but not the other way around.Zizy - Wednesday, June 21, 2017 - link
Well, the corresponding 2P part is >1.1k, so 1P is cheaper. No idea why there isn't 7301P instead and slightly cheaper than the bottom 2P, but I guess that 7351P looks better on the 2P vs 1P.1008anan - Wednesday, June 21, 2017 - link
Trying to calculate how many 32 bit floating point operations (FPO) a zen server completes per second:Assume a 2 socket Zen server with two 32 core chips; operating at 2.5 gigahertz:
512 bits wide vector, Fused Multiply Add, two FPO per clock = 64 FPO per clock = 512/32 * 2 * 2.
64 FPO/clock * 32 cores = 2048 FPO/clock
2048 FPO/clock * 2 sockets = 4096 FPO/clock
4096 FPO/clock * 2.5 gigahertz = 10 trillion FPO/second = 10 teraflops
Is this accurate? Is Zen approximately the same number of FLOPS as Skylake E5/E7?
edzieba - Wednesday, June 21, 2017 - link
An interesting diagram lurking on the corner of this slide: http://images.anandtech.com/doci/11551/epyc_tech_d...Could just be that the diagram is nonsense marketing bling, but that sure looks like external lanes are connected to only two of the 4 cores, with the remaining two getting 'passthrough' lanes.