AMD Zen Microarchitecture: Dual Schedulers, Micro-Op Cache and Memory Hierarchy Revealed
by Ian Cutress on August 18, 2016 9:00 AM ESTLow Power, FinFET and Clock Gating
When AMD launched Carrizo and Bristol Ridge for notebooks, one of the big stories was how AMD had implemented a number of techniques to improve power consumption and subsequently increase efficiency. A number of those lessons have come through with Zen, as well as a few new aspects in play due to the lithography.
First up is the FinFET effect. Regular readers of AnandTech and those that follow the industry will already be bored to death with FinFET, but the design allows for a lower power version of a transistor at a given frequency. Now of course everyone using FinFET can have a different implementation which gives specific power/performance characteristics, but Zen on the 14nm FinFET process at Global Foundries is already a known quantity with AMD’s Polaris GPUs which are built similarly. The combination of FinFET with the fact that AMD confirmed that they will be using the density-optimised version of 14nm FinFET (which will allow for smaller die sizes and more reasonable efficiency points) also contributes to a shift of either higher performance at the same power or the same performance at lower power.
AMD stated in the brief that power consumption and efficiency was constantly drilled into the engineers, and as explained in previous briefings, there ends up being a tradeoff between performance and efficiency about what can be done for a number of elements of the core (e.g. 1% performance might cost 2% efficiency). For Zen, the micro-op cache will save power by not having to go further out to get instruction data, improved prefetch and a couple of other features such as move elimination will also reduce the work, but AMD also states that cores will be aggressively clock gated to improve efficiency.
We saw with AMD’s 7th Gen APUs that power gating was also a target with that design, especially when remaining at the best efficiency point (given specific performance) is usually the best policy. The way the diagram above is laid out would seem to suggest that different parts of the core could independently be clock gated depending on use (e.g. decode vs FP ports), although we were not able to confirm if this is the case. It also relies on having very quick (1-2 cycle) clock gating implementations, and note that clock gating is different to power-gating, which is harder to implement.
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MonkeyPaw - Thursday, August 18, 2016 - link
Heck, people are forgetting some significant firsts for AMD--the first to bring the IMC and hypertransport to x86. Both were big for the server world, too.smilingcrow - Friday, August 19, 2016 - link
Innovation is good and AMD have had many moments in the sun but let's not forget that Core 2 duo lacked an IMC and still trounced the AMD competition.Good products matter more than innovation and the trick is to turn innovation into good products.
The_Countess - Saturday, August 20, 2016 - link
and lets not forget the first with a on-die memory controller for a x86 CPU. a huge improvement on both the desktop and the server space. it basically is what made more then 2 socket motherboards viable at all.Kevin G - Saturday, August 20, 2016 - link
Intel had a 386 chip with an integrated memory controller back in 90's so AMD wasn't the first to do it even in the x86 segment.looncraz - Saturday, August 20, 2016 - link
Pretty sure they did not, they had memory management techs built-in, but not memory controllers. The 286 had memory management capabilities as well, and so did all of AMD's comparable CPUs, naturally.The_Countess - Sunday, August 21, 2016 - link
that would be the first time i heard about that so: source?Kevin G - Sunday, August 21, 2016 - link
80386EX for the embedded market. Came out in 1994. By this time, it was two generations behind the Pentium so it generated very little fan fair.http://news.softpedia.com/news/Intel-Wants-The-Emb...
Here is a book that includes some details about the 80386EX, though you'll have to do a bit of digging in it:
http://userpages.umbc.edu/~squire/intel_book.pdf
Gigaplex - Thursday, August 18, 2016 - link
"AMD was first with CPU + GPU = APU."Llano came out June 2011. Intel had Westmere (January 2010) and Sandy Bridge (January 2011) before Llano. Even if you discount Westmere since they were separate dies on the same package, Sandy Bridge still got there before Llano.
Mahigan - Thursday, August 18, 2016 - link
https://www.sec.gov/Archives/edgar/data/2488/00011...Intel and AMD have a cross-licensing agreement which covers patents and technologies from both firms allowing both firms to use a rather generous amount of patents from their competitor.
Nobody copied nobody. The two companies are quite intertwined tbh.
Mahigan - Thursday, August 18, 2016 - link
"Advanced Micro Devices has clarified terms of the cross-license agreement with Intel Corp. on Thursday. As it appears, if either AMD or Intel change their control (i.e., gets acquired), the cross-license agreement between the two companies is automatically terminated for both parties.AMD and Intel have a cross-licensing agreement, which guarantees that the companies will not pursue litigation for any potential patent infringements. The agreement covers entire patent portfolio for both companies, which includes general-purpose processors, graphics adapters and other intellectual property. For example, AMD can design and sell microprocessors compatible with Intel’s x86 instruction set architecture and featuring a variety of extensions, whereas Intel can develop and ship central processing units that utilize IP and extensions initially created by AMD . The cross-licensing agreement has a number of terms and limitations. For example, the chip designers are not allowed to build processors that are compatible with competitor’s infrastructure (e.g., sockets, mainboards, etc.). Besides, if AMD and Intel change their ownership , the agreement terminated."
http://www.kitguru.net/components/cpu/anton-shilov...