Low Power, FinFET and Clock Gating

When AMD launched Carrizo and Bristol Ridge for notebooks, one of the big stories was how AMD had implemented a number of techniques to improve power consumption and subsequently increase efficiency. A number of those lessons have come through with Zen, as well as a few new aspects in play due to the lithography.

First up is the FinFET effect. Regular readers of AnandTech and those that follow the industry will already be bored to death with FinFET, but the design allows for a lower power version of a transistor at a given frequency. Now of course everyone using FinFET can have a different implementation which gives specific power/performance characteristics, but Zen on the 14nm FinFET process at Global Foundries is already a known quantity with AMD’s Polaris GPUs which are built similarly. The combination of FinFET with the fact that AMD confirmed that they will be using the density-optimised version of 14nm FinFET (which will allow for smaller die sizes and more reasonable efficiency points) also contributes to a shift of either higher performance at the same power or the same performance at lower power.

AMD stated in the brief that power consumption and efficiency was constantly drilled into the engineers, and as explained in previous briefings, there ends up being a tradeoff between performance and efficiency about what can be done for a number of elements of the core (e.g. 1% performance might cost 2% efficiency). For Zen, the micro-op cache will save power by not having to go further out to get instruction data, improved prefetch and a couple of other features such as move elimination will also reduce the work, but AMD also states that cores will be aggressively clock gated to improve efficiency.

We saw with AMD’s 7th Gen APUs that power gating was also a target with that design, especially when remaining at the best efficiency point (given specific performance) is usually the best policy. The way the diagram above is laid out would seem to suggest that different parts of the core could independently be clock gated depending on use (e.g. decode vs FP ports), although we were not able to confirm if this is the case. It also relies on having very quick (1-2 cycle) clock gating implementations, and note that clock gating is different to power-gating, which is harder to implement.

Deciphering the New Cache Hierarchy: L1, 512 KB L2, 8 or 16 MB L3 Simultaneous Multi-Threading, Time Frame
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  • Jleppard - Thursday, August 18, 2016 - link

    OR the first to 5 GHz Reply
  • Kevin G - Saturday, August 20, 2016 - link

    IBM hit 5 Ghz back in 2008 with the POWER6. Reply
  • JlHADJOE - Sunday, August 21, 2016 - link

    Given how quickly they were able to implement x86_64, my bet is Intel already thought about extending x86 to 64bits, they just didn't want to do it because they were pushing Itanium hard at the time.

    But then AMD comes out with AMD64, and (rather predictably) the market loves it, which puts a real damper on Intel's Itanium push and eventually they are forced to capitulate and follow suit.
    Reply
  • hansmuff - Thursday, August 18, 2016 - link

    Everyone copies success, what's new? Reply
  • bill.rookard - Thursday, August 18, 2016 - link

    Well, it's not a complete copy. There are some difference which should make it interesting to see how the chips line up against each other. x2 L2 cache on Zen vs x2 L3 cache on Intel, the larger core/thread counts (let's hope they offer the 8c/16t to consumers), and of course, the big one being how this all affects the integrated graphics in APU form.

    Will the change to 16nm FinFET allow them to put in more GPU? What kind of clocks and/or power envelope will this run at? A lot of this makes a huge difference in the types of systems which can be made - a powerful hex-core CPU with a beefier IGP in a 60-80w TDP would be nice to see.
    Reply
  • smilingcrow - Thursday, August 18, 2016 - link

    There is definitely gong to be a consumer 8c/16t chip. Reply
  • Ian Cutress - Thursday, August 18, 2016 - link

    The 8c will be coming to consumers in the AM4 chipset in Q1. :) Reply
  • Flunk - Thursday, August 18, 2016 - link

    I wonder what the resale value of my 6700K and Z170 board will be in Q1 ;). Reply
  • Morawka - Thursday, August 18, 2016 - link

    you'll get more cores but not more IPC. all signs point to skylake being at least 2 years ahead of zen, although since intel has barely increased performance in 2 years, it shouldnt make to big of a difference, in gaming at least. Reply
  • tamalero - Friday, August 19, 2016 - link

    Disagree, the performance boost of each generation is always less than 5% in the last designs by intel.
    Only a few tests show really higher performance per clock.
    Reply

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