Intel Developer Forum Fall 2002 - Day 1: May the show begin

Itanium 2

Intel finished off the keynote with a quick demonstration of Madison, the ~500 million transistor 0.13-micron successor to Itanium 2. The extremely high transistor count of Madison comes from its on-die 6MB L3 cache; in another year we’ll probably be hearing about the 12MB L3 cache of Montecito. As a recap, here’s Intel’s Itanium line as we know it (taken from Spring IDF 2002):

McKinley (Itanium 2) - The successor to Itanium is pretty well known already. McKinley has been in pilot systems since late last year and is already running at 1GHz. The CPU has a 3MB on-die L3 cache, an 8-stage pipeline, 2 additional issue ports more integer and load/store units, finally the CPU will have a 128-bit FSB running at 100MHz quad-pumped.

Madison - The move to 0.13-micron will occur in 2003 with Madison which will feature up to an incredible 6MB L3 cache located on-die. Madison will be pin-compatible with McKinley.

Deerfield - Also based on Intel's 0.13-micron process, Deerfield will have less L3 cache than Madison and will be aimed at the entry-level IA-64 market in dual processor configurations only. Deerfield will also be made available in 2003.

Montecito - In 2004 we'll see the first 0.09-micron IA-64 processor from Intel codenamed Montecito. Very little is known about it other than the fact that it will have improved architectural features while maintaining platform & software compatibility with McKinley and Madison/Deerfield.

Final Words

That's it for now, we'll have more coverage from the show later tonight including information on DDR-II, Serial ATA and the first pictures of PCI Express.